In semiconductor manufacturing, a semiconductor wafer often undergoes many processing steps or stages before a completed die is formed. For example, lithographic processes are performed on the semiconductor wafer using a mask and photoresist to transfer a particular design or layout onto the wafer. Design Rules (DRs) are a series of parameters provided by semiconductor manufacturers that enable a designer to verify the correctness of a mask or mask set. Design rules are often specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to, among other things, ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the resultant components work as designed.
Conventional basic design rules 10 are illustrated in FIG. 1 for single-layer rules. A width rule 12 specifies the minimum width of any shape or object 14 in the design. A spacing rule 16 specifies the minimum distance between two adjacent shapes or objects 14. Such rules typically exist for each layer formed in the semiconductor manufacturing process, with the lowest layers having the smallest rules, and the highest metal layers having larger rules.
A two-layer rule specifies a relationship that should exist between two layers. For example, an enclosure rule 18 can specify that an object 20 of one type, such as a contact or via, must be covered, with some additional margin, by a metal layer 22. Other design rules, such as minimum area rules are also utilized. Minimum area rules designate a minimum area to be masked or formed, while antenna rules are more complex rules that check ratios of areas of multiple layers of a net for configurations that can result in problems when intermediate layers are etched. Various other design rules can also be provided by the semiconductor manufacturer.
Design Rule Checking (DRC) further determines whether the physical layout of a particular chip layout satisfies a series of Design Rules. Design rule checking is a major step during physical verification signoff on the design, and can also involve a Layout Versus Schematic (LVS) check, XOR Checks, Electrical Rule Check (ERC) and Antenna Checks. For advanced processes some fabs also insist upon the use of more restricted rules to improve yield.
Over time, device sizes are becoming smaller and smaller, and design rule sets have become increasingly more complex with each subsequent generation of semiconductor process. As such, extensive periods of time are spent design rule checking and manually examining statistics associated with the design rules and DRCs.